This present invention relates to analog-to-digital converter (hereinafter xe2x80x9cADCxe2x80x9d) systems and, more particularly, to an apparatus and method for providing a noise-shaped interstage gain error.
A conventional multi-bit per stage, pipelined ADC 10 is shown in FIG. 1. Four stages 12, 14, 16, 18 are shown; however, as shown by ellipsis 20, further stages may be included. An analog input signal VIN is provided on line 22 to stage one 12. A first residual signal VRES1 is provided on line 24 from stage one 12 to stage two 14. A second residual signal VRES2 is provided on line 26 from stage two 14 to stage three 16. A third residual signal VRES3 is provided on line 28 from stage three 16 to stage four 18. A further residual signal is provided from stage four 18 on line 30, and so forth.
Typically, all of the stages of a pipelined ADC such as ADC 10 are the same. In FIG. 1, the functional components of stage two 14 are shown by way of example. Thus, referring to the blowup 15 of stage two 14, input line 24 can be seen, which is an input to sample and hold amplifier (xe2x80x9cSHAxe2x80x9d) 32. The output of SHA 32 is provided on line 34 to an m-bit analog-to-digital subconverter (ADSC) 36, which is typically a flash ADC, and to a first input of a summing unit 38. The output of m-bit ADSC 36 is an m-bit sub-word, which is provided on line 40 both as an output to stage two 14 and is provided as an input to m-bit digital-to-analog subconverter (DASC) 42. The output of m-bit DASC 42 is provided on line 44 to a subtracting input to summing unit 38. The output of summing unit 38 is provided on line 46 to a 2m amplifier 48, which has a theoretical gain of 2m . The output of 2m amplifier 48 is provided on line 26.
In operation, stage two 14 operates as follows. An analog signal is provided on line 24 to SHA 32. SHA 32 samples the analog signal on line 24 at a succession of times and holds each such sample as a signal level on line 34 for a time sufficient to permit m-bit ADSC 36 to sense the level of the signal on line 34 and provided a digital representation thereof, as a sub-word of m-bits, on line 40. Those m-bits are converted to an analog voltage signal by m-bit DASC 42, and provided on line 44. The analog signal on line 44 is subtracted from the input signal on line 34 by summing unit 38, and the difference signal is provided on line 46 to amplifier 48, where it is amplified by a factor of 2m . The difference signal on line 46 represents the negative of the error made by the m-bit ADSC 36. Theoretically, that error signal represents the inaccuracy of the m-bit representation of the analog signal on line 24 due to the limited number of bits. That error signal, amplified by 2m , is input to the following stage of the pipeline via line 26, where a similar set of operations is performed.
After the signal propagates through n stages, a digital sample of the input signal VIN is obtained. Each of the sub-word bit lines provided at the output of the respective stage""s ADSC, e.g., bit lines 40 from ADSC 36, contributes to the overall digital word which is the digital representation provided by ADC 10 of the sampled signal VIN. The sub-word bit lines are concatenated to form this word. A new word is generated for each time period for which a sample is taken in the sample and hold amplifiers, e.g., SHA 32.
In a conventional pipelined ADC, there are three main error sources. The first is the ADSC linearity in the form of comparator offsets. This error can typically be removed by using conventional digital error correction, as described in more detail below. The remaining two error sources are the DASC linearity error and the interstage gain error.
Techniques are known for reducing the DASC linearity error, for example by using a number of dynamic element matching techniques for linearizing the DASC in multiple bit xcexa3-xcex94 ADCs. Examples of such techniques are described in L. R. Carley, xe2x80x9cNoise Shaping Coder Typology for 15-bit Converters,xe2x80x9d IEEE J Solid-State Circuits, S.C. 24 No. 2, pp. 267-273, Apr. 1989; B. H. Leung and S. Sutarja, xe2x80x9cMultibit xcexa3-xcex94 Converter Incorporating a Novel Class of Dynamic Element Matching Techniques,xe2x80x9d IEEE Trans. Circuits and Syst. II, Vol. 39, No. 1, pp. 35-51, Jan. 1992; R. T. Baird and T. Fiez, xe2x80x9cImproved xcexa3-xcex94 DAC Linearity Using Data Weighted Averaging,xe2x80x9d Proc. 1995 IEEE Int. Symp. Circuits Sys., Vol. 1, pp. 13-16, May 1995; and R. Adams and T. Kuan, xe2x80x9cData-Directed Scrambler for Multi-Bit Noise Shaping D/A Converters,xe2x80x9d U.S. Pat. No. 5,404,142, Assigned to Analog Devices, Inc., Apr. 4, 1995. By using a time varying combination of elements to represent the given DASC output level, the element mismatch errors are averaged out over time, thereby linearizing the DASC.
The remaining unsolved problem is the interstage gain error. Therefore, it is an object of the invention to provide a solution to the problem of interstage gain error in multi-bit per stage pipelined ADCs. It is also an object of the present invention to provide a pipelined ADC reducing interstage gain error, as compared with prior art ADCs, while maintaining sufficient simplicity in the overall ADC design so as to permit a commercially viable product including such an ADC.
According to the present invention, there is provided a pipelined analog-to-digital converter for converting an analog signal to a sequence of digital words, each such word representing a value of the analog signal at a time in a succession of times. The converter includes a sequence of analog-to-digital converter stages, each such stage generating at least one bit for each such word. A first such stage in the sequence receives the analog signal, and each such stage subsequent to the first stage receives a residue signal from a previous stage in the sequence. Each such stage includes an analog-to-digital unit that senses a sample of the analog signal and provides one or more bits representing a value of the sample. In at least one of the stages the analog-to-digital unit comprises a xcexa3-xcex94 converter.
These and other features of the invention will be apparent to those skilled in the art from the following detailed description of the invention, taken together with the accompanying drawings.